View M58BW032DB45T3T_1357925.PDF datasheet online --- IC-ON-LINE

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1/60 preliminary data november 2004 this is preliminary information on a new product now in devel opment or undergoing evaluation. de tails are subject to change wit hout notice. m58bw032bt, m58bw032bb m58bw032dt, m58bw032db 32 mbit (1mb x32, boot block, burst) 3.3v supply flash memory features summary supply voltage ?v dd = 3.0v to 3.6v for program, erase and read ?v ddq = v ddqin = 1.6v to 3.6v for i/o buffers high performance ? access time: 45, 55 and 60ns ? 75mhz effective zero wait-state burst read ? synchronous burst reads ? asynchronous page reads memory organization ? eight 64 kbit small parameter blocks ? four 128kbit large parameter blocks (of which one is otp) ? sixty-two 512kbit main blocks hardware block protection ?wp pin lock program and erase ?v pen signal for program/erase enable software block protection ? tuning protection to lock program and erase with 64-bit user programmable password (m58bw032b version only) security ? 64-bit unique device identifier (uid) fast programming ? write to buffer and program capability optimized for fdi drivers ? common flash interface (cfi) ? fast program/erase suspend feature in each block low power consumption ? 100a typical standby figure 1. packages electronic signature ? manufacturer code: 20h ? top device code m58bw032xt: 8838h ? bottom device code m58bw032xb: 8837h operating temperature range ? automotive (grade 3): ? 40 to 125c ? industrial (grade 6): ? 40 to 90c bga lbga80 (za) 10 x 8 ball array pqfp80 (t)
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 2/60 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. lbga connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. pqfp connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 tuning block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. top boot block addresses, m58bw032bt, m58bw032dt . . . . . . . . . . . . . . . . . . . . . . 11 table 3. bottom boot block addresses, m58bw032bb, m58bw032db . . . . . . . . . . . . . . . . . . . 12 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 address inputs (a0-a19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data inputs/outputs (dq0-dq31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 chip enable (e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output disable (gd ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 reset/power-down (rp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program/erase enable (vpen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 latch enable (l ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 burst clock (k). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 burst address advance (b ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 valid data ready (r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write protect (wp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 supply voltage (v dd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 output supply voltage (v ddq ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input supply voltage (v ddqin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ground (v ss and v ssq ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 don?t use (du) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 not connected (nc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous latch controlled bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous page read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous latch controlled bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db reset/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 synchronous burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. synchronous burst read bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 read select bit (m15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 standby disable bit (m14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 x-latency bits (m13-m11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 y-latency bit (m9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 valid data ready bit (m8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 wrap burst bit (m3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 burst length bit (m2-m0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5. example burst configuration x-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 read memory array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 read query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 erase all main blocks command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 write to buffer and program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 set burst configuration register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 tuning protection unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 tuning protection program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 set block protection configuration register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 clear block protection configuration register command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 10. program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . 27 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 program/ write to buffer and program/tuning protection unlock status (bit 4) . . . . . . . . . . 28 vpen status (bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 4/60 block protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 tuning protection status (bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 6. ac measurement input output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8. asynchronous bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. asynchronous bus read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 9. asynchronous latch controlled bus read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . 34 table 17. asynchronous latch controlled bus read ac characteristics . . . . . . . . . . . . . . . . . . . . 34 figure 10.asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. asynchronous page read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11.asynchronous write ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12.asynchronous latch controlled write ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. asynchronous write and latch controlled write ac characteristics . . . . . . . . . . . . . . . 38 figure 13.synchronous burst read (data valid from ?n? clock rising edge) . . . . . . . . . . . . . . . . . 39 table 20. synchronous burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14.synchronous burst read (data valid from ?n? clock rising edge) . . . . . . . . . . . . . . . . . 40 figure 15.synchronous burst read - continuous - valid data ready output . . . . . . . . . . . . . . . . 41 figure 16.synchronous burst read - burst address advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 17.reset, power-down and power-up ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21. reset, power-down and power-up ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 18.lbga80 10x12mm - 8x10 ball array, 1mm pitch, bottom view package outline . . . . . . 43 table 22. lbga80 10x12mm - 8x10 ball array, 1mm pitch, package mechanical data . . . . . . . . . 43 figure 19.pqfp80 - 80 lead plastic quad flat pack, package outline . . . . . . . . . . . . . . . . . . . . . 44 table 23. pqfp80 - 80 lead plastic quad flat pack, package mechanical data. . . . . . . . . . . . . . 44 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 appendix a.flow charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 20.program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 21.program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . 47 figure 22.block erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 23.erase suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 24.unlock device and change tuning protection code flowchart . . . . . . . . . . . . . . . . . . . 50
5/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 25.unlock device and program a tuning protected block flowchart . . . . . . . . . . . . . . . . . 51 figure 26.unlock device and erase a tuning protected block flowchart . . . . . . . . . . . . . . . . . . . 52 figure 27.power-up sequence to burst the flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 28.command interface and program erase controller flowchart (a) . . . . . . . . . . . . . . . . . 54 figure 29.command interface and program erase controller flowchart (b) . . . . . . . . . . . . . . . . . 55 figure 30.command interface and program erase controller flowchart (c) . . . . . . . . . . . . . . . . . 56 figure 31.command interface and program erase controller flowchart (d) . . . . . . . . . . . . . . . . . 57 figure 32.command interface and program erase controller flowchart (e) . . . . . . . . . . . . . . . . . 58 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 25. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 6/60 summary description the m58bw032b/d is a 32mbit non-volatile flash memory that can be erased electrically at the block level and programmed in-system on a double- word basis using a 3.0v to 3.6v v dd supply for the circuit and a v ddq supply down to 1.6v for the in- put and output buffers. the devices support asynchronous (latch con- trolled and page read) and synchronous bus op- erations. the synchronous burst read interface allows a high data transfer rate controlled by the burst clock, k, signal. it is capable of bursting fixed or unlimited lengths of data. the burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. all writes are asynchronous. on power-up the memory defaults to read mode with an asynchronous bus. the device features an asymmetrical block archi- tecture. the m58bw032b/d has an array of 62 main blocks of 512 kbits each, plus 4 large param- eter blocks of 128kbits each and 8 small parame- ter blocks of 64 kbits each. the large and small parameter blocks are located either at the top (m58bw032bt, m58bw032dt) or at the bottom (m58bw032bb, m58bw032db) of the address space. the first large parameter block is referred to as boot block and can be used either to store a boot code or parameters. the memory array orga- nization is detailed in tables 2 , top boot block ad- dresses and 3 , bottom boot block addresses. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified in the status regis- ter. the command set required to control the memory is consistent with jedec standards. erase can be suspended in order to perform either read or program in any other block and then re- sumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cy- cles. all blocks are protected during power-up. the m58bw032b features four different levels of hard- ware and software block protection to avoid un- wanted program/erase operations: write/protect enable input, wp, provides a hardware protection of a combination of blocks from program or erase operations. the block protection configuration can be defined individually by issuing a set block protection configuration register or clear block protection configuration register commands. all program or erase operations are blocked when reset, rp, is held low. a program/erase enable input, v pen , is used to protect all blocks, preventing program and erase operations from affecting their data. the program and erase commands can be password protected by the tuning protection command. the m58bw032d offers the same protection fea- tures with the exception of the tuning block pro- tection which is disabled in the factory. a reset/power-down mode is entered when the rp input is low. in this mode the power consump- tion is reduced to the standby level, the device is write protected and both the status and burst con- figuration registers are cleared. a recovery time is required when the rp input goes high. a manufacturer and device code are available. they can be read from the memory allowing pro- gramming equipment or applications to automati- cally match their interface to the characteristics of the memory. finally, the m58bw032b/d features a unique de- vice identifier (uid) which is programmed by st. it is unique for each die and can be used to imple- ment cryptographic algorithms to improve securi- ty. the memory is offered in pqfp80 (14 x 20mm) and lbga80 (1.0mm pitch) packages and it is supplied with all the bits erased (set to ?1?).
7/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 2. logic diagram table 1. signal names ai08918b a0-a19 l dq0-dq31 v dd m58bw032dt m58bw032db e v ss rp g gd v ddq w wp r k v pen b v ssq v ddqin m58bw032bt m58bw032bb a0-a19 address inputs dq0-dq7 data input/output, command input dq8-dq15 data input/output, burst configuration register dq16-dq31 data input/output b burst address advance e chip enable g output enable kburst clock l latch enable r valid data ready rp reset /power-down w write enable gd output disable wp write protect v dd supply voltage v ddq power supply for output buffers v ddqin power supply for input buffers only v pen program/erase enable v ss ground v ssq input/output ground nc not connected internally du don?t use as internally connected
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 8/60 figure 3. lbga connections (top view through package) ai08920b b dq24 dq7 v ssq f v ddq dq26 dq4 v ddq e dq29 v ss dq0 dq3 d a0 du a7 a11 a18 a17 c a1 a4 a5 a8 rp e a13 a16 b a2 a3 a6 v dd v pen v dd a14 a 8 7 6 5 4 3 2 1 dq20 dq18 dq19 dq17 dq11 dq12 dq13 v ddq dq23 dq8 v ddq h g du gd w v ddqin dq16 r g l dq14 dq15 k j a15 v ss a12 a9 a10 nc a19 nc dq31 dq30 dq2 dq28 dq6 dq25 v ssq dq10 dq9 dq21 wp k du dq1 dq27 dq5 nc dq22
9/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 4. pqfp connections (top view through package) ai08919c 12 1 73 m58bw032bt m58bw032bb 53 v ddq dq24 dq25 dq18 dq17 dq16 dq19 dq20 dq21 dq22 dq23 v ddq dq29 dq26 dq30 du dq31 dq28 dq27 a2 a5 a3 a4 a0 a1 a11 v ss a12 a13 a14 a10 gd wp w du g v ss e k l nc b rp v ddq dq7 dq6 dq13 dq14 dq15 dq12 dq11 dq10 dq9 v ssq dq8 dq2 dq5 dq0 a19 a18 a16 a17 dq3 dq4 v ssq v ssq a8 a6 a7 v pen v dd a9 a15 dq1 v ddq v ssq r v dd nc v ddqin 24 25 32 40 41 64 65 80 m58bw032dt m58bw032db
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 10/60 block protection the m58bw032b features four different levels of block protection. the m58bw032d has the same block protection with the exception of the tuning block protection, which is disabled in the factory. write protect pin, wp , - when wp is low, v il , the protection status that has been configured in the block protection configuration register is activated. the block protection configuration register is volatile. any combination of blocks is possible. any attempt to program or erase a protected block will be ignored and will return an error in the status register (see table 11., status register bits ). reset/power-down pin, rp , - if the device is held in reset mode (rp at v il ), no program or erase operations can be performed on any block. program/erase enable, v pen , - v pen protects all blocks preventing program and erase operations from affecting their data. program/erase enable must be kept high (v ih ) during all program/erase controller operations, otherwise the operations is not guaranteed to succeed and data may become corrupt. tuning block protection - m58bw032b features a 64 bit password protection for program and erase operations for a fixed number of blocks after power-up or reset the device is tuning protected. an unlock command is provided to allow program or erase operations in all the blocks. after a device reset the first two kinds of block pro- tection (wp , rp ) can be combined to give a flexi- ble block protection. they do not affect the tuning block protection. when the two protections are disabled, wp and rp at v ih , the blocks locked by the tuning block protection cannot be modified. all blocks are protected at power-up. tuning block protection the tuning block protection is a software feature to protect blocks from program or erase opera- tions. it allows the user to lock program and erase operations with a user definable 64 bit code. it is only available on the m58bw032b version. the code is written once in the tuning protection register and cannot be erased. when shipped the flash memory will have the tuning protection code bits set to ?1'. the user can program a ?0? in any of the 64 positions. once programmed it is not possible to reset a bit to ?1? as the cells cannot be erased. the tuning protection register can be programmed at any moment (after providing the correct code), however once all bits are set to ?0? the tuning protection code can no longer be al- tered. the tuning protection code locks the program and erase operations of all the blocks except for blocks 12 and 13 for the bottom configuration, and blocks 60 and 61 for the top configuration. the tuning blocks are "locked" if the tuning protec- tion code has not been provided, and ?unlocked" once the correct code has been provided. the tun- ing blocks are locked after reset or power-up. the tuning protection status can be monitored in the status register. refer to the status register sec- tion. refer to the command interface section for the tuning protection block unlock and tuning pro- tection program commands. see appendix a , fig- ure 24 , 25 and 26 for suggested flowcharts for using the tuning block protection commands.
11/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db table 2. top boot block addresses, m58bw032bt, m58bw032dt note: 1. addresses are indicated in 32-bit addressing. 2. tp = tuning protected block, only available for the m58bw032b. 3. otp block. # size (kbit) address range (1) tp (2) 73 128 ff000h-ffffh yes 72 128 fe000h-fefffh (3) yes 71 128 fd000h-fdfffh yes 70 128 fc000h-fcfffh yes 69 64 fb800h-fbfffh yes 68 64 fb000h-fb7ffh yes 67 64 fa800h-fafffh yes 66 64 fa000h-fa7ffh yes 65 64 f9800h-f9fffh yes 64 64 f9000h-f97ffh yes 63 64 f8800h-f8fffh yes 62 64 f8000h-f87ffh yes 61 512 f4000h-f7fffh no 60 512 f0000h-f3fffh no 59 512 ec000h-effffh yes 58 512 e8000h-ebfffh yes 57 512 e4000h-e7fffh yes 56 512 e0000h-e3fffh yes 55 512 dc000h-dffffh yes 54 512 d8000h-dbfffh yes 53 512 d4000h-d7fffh yes 52 512 d0000h-d3fffh yes 51 512 cc000h-cffffh yes 50 512 c8000h-cbfffh yes 49 512 c4000h-c7fffh yes 48 512 c0000h-c3fffh yes 47 512 bc000h-bffffh yes 46 512 b8000h-bbfffh yes 45 512 b4000h-b7fffh yes 44 512 b0000h-b3fffh yes 43 512 ac000h-affffh yes 42 512 a8000h-abfffh yes 41 512 a4000h-a7fffh yes 40 512 a0000h-a3fffh yes 39 512 9c000h-9ffffh yes 38 512 98000h-9bfffh yes 37 512 94000h-97fffh yes 36 512 90000h-93fffh yes 35 512 8c000h-8ffffh yes 34 512 88000h-8bfffh yes 33 512 84000h-87fffh yes 32 512 80000h-83fffh yes 31 512 7c000h-7ffffh yes 30 512 78000h-7bfffh yes 29 512 74000h-77fffh yes 28 512 70000h-73fffh yes 27 512 6c000h-6ffffh yes 26 512 68000h-6bfffh yes 25 512 64000h-67fffh yes 24 512 60000h-63fffh yes 23 512 5c000h-53ffffh yes 22 512 58000h-5bfffh yes 21 512 54000h-57fffh yes 20 512 50000h-53fffh yes 19 512 4c000h-4ffffh yes 18 512 48000h-4bfffh yes 17 512 44000h-47fffh yes 16 512 40000h-43fffh yes 15 512 3c000h-3ffffh yes 14 512 38000h-3bfffh yes 13 512 34000h-37fffh yes 12 512 30000h-33fffh yes 11 512 2c000h-2ffffh yes 10 512 28000h-2bfffh yes 9 512 24000h-27fffh yes 8 512 20000h-23fffh yes 7 512 1c000h-1ffffh yes 6 512 18000h-1bfffh yes 5 512 14000h-17fffh yes 4 512 10000h-13fffh yes 3 512 0c000h-0ffffh yes 2 512 08000h-0bfffh yes 1 512 04000h-07fffh yes 0 512 00000h-03fffh yes #size (kbit) address range (1) tp (2)
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 12/60 table 3. bottom boot block addresses, m58bw032bb, m58bw032db note: 1. addresses are indicated in 32-bit word addressing. 2. tp = tuning protected block, only available for the m58bw032b. 3. otp block. #size (kbit) address range (1) tp (2) 73 512 fc000h-fffffh yes 72 512 f8000h-fbfffh yes 71 512 f4000h-f7fffh yes 70 512 f0000h-f3fffh yes 69 512 ec000h-effffh yes 68 512 e8000h-ebfffh yes 67 512 e4000h-e7fffh yes 66 512 e0000h-e3fffh yes 65 512 dc000h-dffffh yes 64 512 d8000h-dbfffh yes 63 512 d4000h-d7fffh yes 62 512 d0000h-d3fffh yes 61 512 cc000h-cffffh yes 60 512 c8000h-cbfffh yes 59 512 c4000h-c7fffh yes 58 512 c0000h-c3fffh yes 57 512 bc000h-bffffh yes 56 512 b8000h-bbfffh yes 55 512 b4000h-b7fffh yes 54 512 b0000h-b3fffh yes 53 512 ac000h-affffh yes 52 512 a8000h-abfffh yes 51 512 a4000h-a7fffh yes 50 512 a0000h-a3fffh yes 49 512 9c000h-9ffffh yes 48 512 98000h-9bfffh yes 47 512 94000h-97fffh yes 46 512 90000h-93fffh yes 45 512 8c000h-8ffffh yes 44 512 88000h-8bfffh yes 43 512 84000h-87fffh yes 42 512 80000h-83fffh yes 41 512 7c000h-7ffffh yes 40 512 78000h-7bfffh yes 39 512 74000h-77fffh yes 38 512 70000h-73fffh yes 37 512 6c000h-6ffffh yes 36 512 68000h-6bfffh yes 35 512 64000h-67fffh yes 34 512 60000h-63fffh yes 33 512 5c000h-53ffffh yes 32 512 58000h-5bfffh yes 31 512 54000h-57fffh yes 30 512 50000h-53fffh yes 29 512 4c000h-4ffffh yes 28 512 48000h-4bfffh yes 27 512 44000h-47fffh yes 26 512 40000h-43fffh yes 25 512 3c000h-3ffffh yes 24 512 38000h-3bfffh yes 23 512 34000h-37fffh yes 22 512 30000h-33fffh yes 21 512 2c000h-2ffffh yes 20 512 28000h-2bfffh yes 19 512 24000h-27fffh yes 18 512 20000h-23fffh yes 17 512 1c000h-1ffffh yes 16 512 18000h-1bfffh yes 15 512 14000h-17fffh yes 14 512 10000h-13fffh yes 13 512 0c000h-0ffffh no 12 512 08000h-0bfffh no 11 64 07800h-07fffh yes 10 64 07000h-077ffh yes 9 64 06800h-06fffh yes 8 64 06000h-067ffh yes 7 64 05800h-05fffh yes 6 64 05000h-057ffh yes 5 64 04800h-04fffh yes 4 64 04000h-047ffh yes 3 128 03000h-03fffh yes 2 128 02000h-02fffh yes 1128 01000h-01fffh (3) yes 0 128 00000h-00fffh yes #size (kbit) address range (1) tp (2)
13/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db signal descriptions see figure 2., logic diagram and table 1., signal names , for a brief overview of the signals connect- ed to this device. address inputs (a0-a19). the address inputs are used to select the cells to access in the mem- ory array during bus read operations either to read or to program data to. during bus write oper- ations they control the commands sent to the command interface of the internal state machine. chip enable must be low when selecting the ad- dresses. the address inputs are latched on the rising edge of latch enable l or burst clock k, whichever oc- curs first, in a read operation.the address inputs are latched on the rising edge of chip enable, write enable or latch enable, whichever occurs first in a write operation. the address latch is transparent when latch enable is low, v il . the address is internally latched in an erase or pro- gram operation. data inputs/outputs (dq0-dq31). the data in- puts/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. dur- ing bus write operations they represent the com- mands sent to the command interface of the internal state machine. when used to input data or write commands they are latched on the rising edge of write enable or chip enable, whichever occurs first. when chip enable and output enable are both low, v il , and output disable is at v ih, the data bus outputs data from the memory array, the elec- tronic signature, the block protection configura- tion register, the cfi information or the contents of burst configuration register or status register. the data bus is high impedance when the device is deselected with chip enable at v ih , output en- able at v ih , output disable at v il or reset/power- down at v il . the status register content is output on dq0-dq7 and dq8-dq31 are at v il . chip enable (e ). the chip enable, e , input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. chip enable, e , at v ih deselects the memory and reduces the power consumption to the standby level. output enable (g ). the output enable, g , gates the outputs through the data output buffers during a read operation, when output disable gd is at v ih . when output enable g is at v ih , the outputs are high impedance independently of output dis- able. output disable (gd ). the output disable, gd , deactivates the data output buffers. when output disable, gd , is at v ih , the outputs are driven by the output enable. when output disable, gd , is at v il , the outputs are high impedance indepen- dently of output enable. the output disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin. write enable (w ). the write enable, w , input controls writing to the command interface, input address and data latches. both addresses and data can be latched on the rising edge of write en- able (also see latch enable, l ). reset/power-down (rp ). the reset/power- down, rp , is used to apply a hardware reset to the memory. a hardware reset is achieved by holding reset/power-down low, v il , for at least t plph . writing is inhibited to protect data, the command interface and the program/erase controller are re- set. the status register information is cleared and power consumption is reduced to the standby level (i dd1 ). the device acts as deselected, that is the data outputs are high impedance. after reset/power-down goes high, v ih , the memory will be ready for bus read operations af- ter a delay of t phel or bus write operations after t phwl . if reset/power-down goes low, v il , during a block erase, a program or a tuning protection program the operation is aborted, in a time of t pl- rh maximum, and data is altered and may be cor- rupted. during power-up power should be applied simulta- neously to v dd and v ddq(in) with rp held at v il . when the supplies are stable rp is taken to v ih . output enable, g , chip enable, e , and write en- able, w , should be held at v ih during power-up. in an application, it is recommended to associate reset/power-down pin, rp , with the reset signal of the microprocessor. otherwise, if a reset opera- tion occurs while the memory is performing an erase or program operation, the memory may out- put the status register information instead of be- ing initialized to the default asynchronous random read. see table 21 and figure 17., reset, power-down and power-up ac waveform , for more details. program/erase enable (v pen ). the program./ erase enable input, v pen , protects all blocks, pre- venting program and erase operations from mod- ifying the data. program/erase enable must be kept high (v ih ) during all operations when the pro- gram/erase controller is active, otherwise the op- eration is not guaranteed to succeed and data may become corrupt. latch enable (l ). the bus interface can be con- figured to latch the address inputs on the rising edge of latch enable, l , for asynchronous latch
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 14/60 enable controlled read or write or synchronous burst read operations. in synchronous burst read operations the address is latched on the ac- tive edge of the clock when latch enable is low, v il . once latched, the addresses may change without affecting the address used by the memory. when latch enable is low, v il , the latch is trans- parent. latch enable, l , can remain at v il for asynchronous random read and write opera- tions. burst clock (k). the burst clock, k, is used to synchronize the memory with the external bus dur- ing synchronous burst read operations. bus sig- nals are latched on the active edge of the clock. in synchronous burst read mode the address is latched on the first rising clock edge when latch enable is low, v il , or on the rising edge of latch enable, whichever occurs first. during asynchronous bus operations the clock is not used. burst address advance (b ). the burst address advance, b , controls the advancing of the address by the internal address counter during synchro- nous burst read operations. burst address advance, b , is only sampled on the active clock edge of the clock when the x-latency time has expired. if burst address advance is low, v il , the internal address counter advances. if burst address advance is high, v ih , the internal address counter does not change; the same data remains on the data inputs/outputs and burst ad- dress advance is not sampled until the y-latency expires. the burst address advance, b , may be tied to v il . valid data ready (r). the valid data ready output, r, can be used during synchronous burst read operations to identify if the memory is ready to output data or not. the valid data ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. valid data ready, at v ih , indicates that new data is or will be available. when valid data ready is low, v il , the previous data outputs remain active. write protect (wp ). the write protect, wp , pro- vides protection against program or erase opera- tions. when write protect, wp , is at v il , the protection status that has been configured in the block protection configuration register is activat- ed. program and erase operations to protected blocks are disabled. when write protect wp is at v ih all the blocks can be programmed or erased, if no other protection is used. supply voltage (v dd ). the supply voltage, v dd , is the core power supply. all internal circuits draw their current from the v dd pin, including the pro- gram/erase controller. output supply voltage (v ddq ). the output sup- ply voltage, v ddq , is the output buffer power supply for all operations (read, program and erase) used for dq0-dq31 when used as outputs. input supply voltage (v ddqin ). the input sup- ply voltage, v ddin , is the power supply for all input signal. input signals are: k, b , l , w , gd , g , e , a0- a18 and d0-d31, when used as inputs. ground (v ss and v ssq ). the ground v ss is the reference for the internal supply voltage v dd . the ground v ssq is the reference for the output and input supplies v ddq, and v ddqin . it is essential to connect v ss and v ssq together. note: a 0.1 f capacitor should be connected between the supply voltages, v dd , v ddq and v ddin and the grounds, v ss and v ssq to decou- ple the current surges from the power supply. the pcb track widths must be sufficient to car- ry the currents required during all operations of the parts, see table 15., dc characteristics , for maximum current supply requirements. don?t use (du). this pin should not be used as it is internally connected. its voltage level can be be- tween v ss and v ddq or leave it unconnected. not connected (nc). this pin is not physically connected to the device.
15/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db bus operations each bus operations that controls the memory is described in this section, see tables 4 and 5 bus operations, for a summary. the bus operation is selected through the burst configuration register; the bits in this register are described at the end of this section. on power-up or after a hardware reset the mem- ory defaults to asynchronous bus read and asyn- chronous bus write. no synchronous operation can be performed until the burst control register has been configured. the electronic signature, block protection config- uration, cfi or status register will be read in asynchronous mode regardless of the burst con- trol register settings. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. asynchronous bus operations for asynchronous bus operations refer to table 4 together with the following text. asynchronous bus read. asynchronous bus read operations read from the memory cells, or specific registers (electronic signature, block pro- tection configuration register, status register, cfi and burst configuration register) in the com- mand interface. a valid bus operation involves set- ting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable and out- put disable high, v ih . the data inputs/outputs will output the value, see figure 8., asynchronous bus read ac waveforms , and table 16., asynchronous bus read ac characteristics. , for details of when the output becomes valid. asynchronous read is the default read mode which the device enters on power-up or on return from reset/power-down. asynchronous latch controlled bus read. asynchronous latch controlled bus read opera- tions read from the memory cells or specific regis- ters in the command interface. the address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. a valid bus operation involves setting the desired address on the address inputs, setting chip en- able and latch enable low, v il and keeping write enable high, v ih ; the address is latched on the ris- ing edge of latch enable. once latched, the ad- dress inputs can change. set output enable low, v il , to read the data on the data inputs/outputs; see figure figure 9., asynchronous latch con- trolled bus read ac waveforms and table 17., asynchronous latch controlled bus read ac characteristics , for details on when the output be- comes valid. note that, since the latch enable input is transpar- ent when set low, v il , asynchronous bus read operations can be performed when the memory is configured for asynchronous latch enable bus operations by holding latch enable low, v il throughout the bus operation. asynchronous page read. asynchronous page read operations are used to read from sev- eral addresses within the same memory page. each memory page is 4 double-words and is ad- dressed by the address inputs a0 and a1. data is read internally and stored in the page buff- er. valid bus operations are the same as asyn- chronous bus read operations but with different timings. the first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings ap- ply again. page read does not support latched controlled read. see figure 10., asynchronous page read ac waveforms , and table 18., asynchronous page read ac characteristics , for details on when the outputs become valid. asynchronous bus write. asynchronous bus write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. bus write operations are asynchronous, the clock, k, is don?t care during bus write operations. a valid asynchronous bus write operation begins by setting the desired address on the address in- puts, and setting chip enable, write enable and latch enable low, v il , and output enable high, v ih , or output disable low, v il . the address in- puts are latched by the command interface on the rising edge of chip enable or write enable, which- ever occurs first. commands and input data are latched on the rising edge of chip enable, e , or write enable, w , whichever occurs first. output enable must remain high, and output disable low, during the whole asynchronous bus write operation. see figure 11., asynchronous write ac wave- form , and asynchronous write and latch con- trolled write ac characteristics , for details of the timing requirements.
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 16/60 asynchronous latch controlled bus write. asynchronous latch controlled bus write opera- tions write to the command interface in order to send commands to the memory or to latch ad- dresses and input data to program. bus write op- erations are asynchronous, the clock, k, is don?t care during bus write operations. a valid asynchronous latch controlled bus write operation begins by setting the desired address on the address inputs and pulsing latch enable low, v il . the address inputs are latched by the com- mand interface on the rising edge of latch enable, write enable or chip enable, whichever occurs first. commands and input data are latched on the rising edge of chip enable, e , or write enable, w , whichever occurs first. output enable must remain high, and output disable low, during the whole asynchronous bus write operation. see figure 12., asynchronous latch controlled write ac waveform , and table 19., asynchronous write and latch controlled write ac characteristics , for details of the timing requirements. output disable. the data outputs are high im- pedance when the output enable, g , is at v ih or output disable, gd , is at v il . standby. when chip enable is high, v ih , and the program/erase controller is idle, the memory en- ters standby mode, the power consumption is re- duced to the standby level (i dd1 ) and the data inputs/outputs pins are placed in the high imped- ance state regardless of output enable, write en- able or output disable inputs. the standby mode can be disabled by setting the standby disable bit (m14) of the burst configura- tion register to ?1? (see table 15., dc character- istics ). reset/power-down. the memory is in reset/ power-down mode when reset/power-down, rp , is at v il . the power consumption is reduced to the standby level (i dd1 ) and the outputs are high impedance, independent of the chip enable, e , output enable, g , output disable, gd , or write enable, w, inputs. in this mode the device is write protected and both the status and the burst con- figuration registers are cleared. a recovery time is required when the rp input goes high. table 4. asynchronous bus operations note: 1. x = don?t care 2. data, manufacturer code, device code, burst configuration r egister, standby status and block protection configuration registe r are read using the asynchronous bus read command. bus operation step e g gd w rp l a0-a19 dq0-dq31 asynchronous bus read (2) v il v il v ih v ih v ih v il address data output asynchronous latch controlled bus read address latch v il v ih v ih v il v ih v il address high z read v il v il v ih v ih v ih v ih x data output asynchronous page read v il v il v ih v ih v ih x address data output asynchronous bus write v il v ih x v il v ih v il address data input asynchronous latch controlled bus write address latch v il v ih x v ih v ih v il address high z write v il v ih x v il v ih v ih x data input output disable, g v il v ih v ih v ih v ih xx high z output disable, gd v il v il v il v ih v ih xx high z standby v ih xxx v ih xx high z reset/power-down x x x x v il xx high z
17/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db synchronous bus operations for synchronous bus operations refer to table 5 together with the following text. synchronous burst read. synchronous burst read operations are used to read from the memo- ry at specific times synchronized to an external ref- erence clock. the valid edge of the clock signal is the rising edge. the burst type, length and latency can be configured. the different configurations for synchronous burst read operations are de- scribed in the burst configuration register sec- tion. refer to figure 5 for examples of synchronous burst operations. in continuous burst read, one burst read operation can access the entire memory sequentially by keeping the burst address advance b at v il for the appropriate number of clock cycles. at the end of the memory address space the burst read re- starts from the beginning at address 000000h. a valid synchronous burst read operation begins when the burst clock is active and chip enable and latch enable are low, v il . the burst start ad- dress is latched and loaded into the internal burst address counter on the valid burst clock k edge or on the rising edge of latch enable, whichever occurs first. after an initial memory latency time, the memory outputs data each clock cycle (or two clock cycles depending on the value of m9). the burst address advance b input controls the memory burst output. the second burst output is on the next clock valid edge after the burst address advance b has been pulled low. valid data ready, r, monitors if the memory burst boundary is exceeded and the burst controller of the microprocessor needs to insert wait states. when valid data ready is low on the rising clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if burst address ad- vance, b , is low. valid data ready may be configured (by bit m8 of burst configuration register) to be valid immedi- ately at the rising clock edge or one data cycle be- fore the rising clock edge. synchronous burst read will be suspended if burst address advance, b , goes high, v ih . if output enable is at v il and output disable is at v ih , the last data is still valid. if output enable, g , is at v ih or output disable, gd , is at v il , but the burst address advance, b , is at v il the internal burst address counter is incre- mented at each burst clock k rising edge. the synchronous burst read timing diagrams and ac characteristics are described in the ac and dc parameters section. see figures 13 , 14 , 15 and 16 , and table 20 . synchronous burst read suspend. during a synchronous burst read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. a valid synchronous burst read operation is sus- pended when both output enable and burst ad- dress advance are high, v ih . the burst address advance going high, v ih , stops the burst counter and the output enable going high, v ih , inhibits the data outputs. the synchronous burst read oper- ation can be resumed by setting output enable low. table 5. synchronous burst read bus operations note: 1. x = don't care, v il or v ih . 2. m15 = 0, bit m15 is in the burst configuration register. 3. r= rising edge. bus operation step e g gd rp kl b a0-a19 dq0-dq31 synchronous burst read (2) address latch v il v ih x v ih r (3) v il x address input read v il v il v ih v ih r (3) v ih v il data output read suspend v il v ih x v ih x v ih v ih high z read resume v il v il v ih v ih r (3) v ih v il data output burst address advance v il v ih x v ih r (3) v ih v il high z read abort, e v ih xx v ih xxx high z read abort, rp xxx v il xxx high z
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 18/60 burst configuration register the burst configuration register is used to config- ure the type of bus access that the memory will perform. the burst configuration register is set through the command interface and will retain its informa- tion until it is re-configured, the device is reset, or the device goes into reset/power-down mode. the burst configuration register bits are de- scribed in table 6 . they specify the selection of the burst length, burst type, burst x and y laten- cies and the read operation. refer to figure 5 for examples of synchronous burst configurations. read select bit (m15). the read select bit, m15, is used to switch between asynchronous and synchronous bus read operations. when the read select bit is set to ?1?, bus read operations are asynchronous; when the read select but is set to ?0?, bus read operations are synchronous. on reset or power-up the read select bit is set to?1? for asynchronous accesses. standby disable bit (m14). the standby dis- able bit, m14, is used to disable the standby mode. when the standby bit is ?1?, the device will not enter standby mode when chip enable goes high, v ih . x-latency bits (m13-m11). the x-latency bits are used during synchronous bus read opera- tions to set the number of clock cycles between the address being latched and the first data be- coming available. for correct operation the x-la- tency bits can only assume the values in table 6., burst configuration register . the x-latency bits should also be selected in accordance with note: 1. below table 6., burst configuration reg- ister . y-latency bit (m9). the y-latency bit is used during synchronous bus read operations to set the number of clock cycles between consecutive reads. the y-latency value depends on both the x-latency value and the setting in m9. when the y-latency is 1 the data changes each clock cycle; when the y-latency is 2 the data changes every second clock cycle. see table 6., burst configuration register and note 2. for valid combinations of the y-latency, the x-laten- cy and the clock frequency. valid data ready bit (m8). the valid data ready bit controls the timing of the valid data ready output pin, r. when the valid data ready bit is ?0? the valid data ready output pin is driven low for the rising clock edge when invalid data is output on the bus. when the valid data ready bit is ?1? the valid data ready output pin is driven low one clock cycle prior to invalid data being output on the bus. wrap burst bit (m3). the burst reads can be confined inside the 4 or 8 word boundary (wrap) or overcome the boundary (no wrap). the wrap burst bit is used to select between wrap and no wrap. when the wrap burst bit is set to ?0? the burst read wraps; when it is set to ?1? the burst read does not wrap. burst length bit (m2-m0). the burst length bits set the maximum number of double-words that can be output during a synchronous burst read operation before the address wraps. burst lengths of 4 or 8 and continuous burst are available. table 6., burst configuration register gives the valid combinations of the burst length bits that the memory accepts; table 7., burst type definition , gives the sequence of addresses output from a given starting address for each length. if either a continuous or a no wrap burst read has been initiated the device will output data syn- chronously. depending on the starting address, the device activates the valid data ready output to indicate that a delay is necessary before the data is output. if the starting address is aligned to a 4 double word boundary, the continuous burst mode will run without activating the valid data ready output. if the starting address is not aligned to a 4 double word boundary, valid data ready is activated to indicate that the device needs an in- ternal delay to read the successive words in the ar- ray. m10, m7 to m4 are reserved for future use.
19/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db table 6. burst configuration register note: 1. x latencies can be calculated as: (t avqv ? t llkh + t khqv ) + t system margin < (x -1) t k. (x is an integer number from 4 to 8 and t k is the clock period), , where t llkh is the value given by the master microcontroller timing specifications. 2. y latencies can be calculated as: t khqv + t system margin + t khqv < y t k . 3. t system margin is the time margin required for the calculation. bit description value description m15 read select 0 synchronous burst read 1 asynchronous read (default at power-up) m14 standby disable 0 standby mode enabled (default at power-up) 1 standby mode disabled m13-m11 x-latency (1) 001 3 010 4 011 5 100 6 101 7 110 8 m10 reserved m9 y-latency (2) 0 one burst clock cycle 1 two burst clock cycles m8 valid data ready 0 r valid low during valid burst clock edge 1 r valid low one data cycle before valid burst clock edge m7-m4 reserved m3 wrapping 0wrap 1no wrap m2-m0 burst length 001 4 double-words 010 8 double-words 111 continuous
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 20/60 table 7. burst type definition m 3 starting address x4 sequential x8 sequential continuous 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10.. 0 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11.. 0 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12.. 0 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13.. 0 4 ? 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-2-13-14.. 0 5 ? 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14.. 0 6 ? 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15.. 0 7 ? 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-16.. 0 8 ? ? 8-9-10-11-12-13-14-15-16-17.. 1 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10.. 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11.. 1 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12.. 1 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13.. 1 4 4-5-6-7 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14.. 1 5 5-6-7-8 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-14.. 1 6 6-7-8-9 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-15.. 1 7 7-8-9-10 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-15-16.. 1 8 8-9-10-11 8-9-10-11-12-13-14-15 8-9-10-11-12-13-14-15-16-17..
21/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 5. example burst configuration x-1-1-1 ai03841b k dq l add valid dq dq dq dq 4-1-1-1 5-1-1-1 6-1-1-1 7-1-1-1 8-1-1-1 0123456789 valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid dq 3-1-1-1 valid valid valid valid valid valid valid
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 22/60 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. the commands are summarized in table 8., commands . refer to table 8 in conjunction with the text descriptions below. read memory array command the read memory array command returns the memory to read mode. one bus write cycle is re- quired to issue the read memory array command and return the memory to read mode. subse- quent read operations will output the addressed memory array data. once the command is issued the memory remains in read mode until another command is issued. from read mode bus read commands will access the memory array. read electronic signature command the read electronic signature command is used to read the manufacturer code, the device code, the block protection configuration register and the burst configuration register. one bus write cycle is required to issue the read electronic sig- nature command. once the command is issued, subsequent bus read operations, depending on the address specified, read the manufacturer code, the device code, the block protection con- figuration or the burst configuration register until another command is issued; see table 9., read electronic signature . read query command the read query command is used to read data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read query command. once the command is is- sued subsequent bus read operations, depend- ing on the address specified, read from the common flash interface memory area. read status register command the read status register command is used to read the status register. one bus write cycle is required to issue the read status register com- mand. once the command is issued subsequent bus read operations read the status register un- til another command is issued. the status register information is present on the output data bus (dq0-dq7) when chip enable e and output enable g are at v il and output dis- able is at v ih . an interactive update of the status register bits is possible by toggling output enable or output dis- able. it is also possible during a program or erase operation, by disactivating the device with chip enable at v ih and then reactivating it with chip en- able and output enable at v il and output disable at v ih . the content of the status register may also be read at the completion of a program, erase or suspend operation. during a block erase, pro- gram, tuning protection program or tuning pro- tection unlock command, dq7 indicates the program/erase controller status. it is valid until the operation is completed or suspended. see the section on the status register and table 11 for details on the definitions of the status reg- ister bits. clear status register command the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register to ?0?. one bus write is required to issue the clear status register command. once the command is issued the memory returns to its previous mode, subsequent bus read operations continue to out- put the same data. the bits in the status register are sticky and do not automatically return to ?0? when a new pro- gram, erase, block protect or block unprotect command is issued. if any error occurs then it is essential to clear any error bits in the status reg- ister by issuing the clear status register com- mand before attempting a new program, erase or resume command. block erase command the block erase command can be used to erase a block. it sets all of the bits in the block to ?1?. all previous data in the block is lost. if the block is pro- tected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write operations are required to issue the command; the first write cycle sets up the block erase command, the second write cycle confirms the block erase command and latches the block address in the internal state machine and starts the program/erase controller. the sequence is aborted if the confirm command is not given and the device will output the status register data with bits 4 and 5 set to '1'. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the erase operation the memory will only accept the read status register command and the program/ erase suspend command. all other commands will be ignored. the command can be executed using v dd . if v pen is at v ih , the operation can be performed. if v pen goes below v ih, the operation aborts, the v pen status bit in the status register is set to ?1? and the command must be re-issued.
23/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db typical erase times are given in table 10 . see appendix a , figure 22., block erase flow- chart and pseudo code , for a suggested flowchart on using the block erase command. erase all main blocks command the erase all main blocks command is used to erase all 63 main blocks, without affecting the pa- rameter blocks. issuing the erase all main blocks command sets every bit in each main block to '1'. all data previ- ously stored in the main blocks are lost. two bus write cycles are required to issue the erase all main blocks command. the first cycle sets up the command, the second cycle confirms the command and starts the program/erase con- troller. if the confirm command is not given the sequence is aborted, and status register bits 4 and 5 are set to '1'. if the address given in the second cycle is located in a protected block, the erase all main blocks op- eration aborts. the data remains unchanged in all blocks and the status register outputs the error. once the erase all main blocks command has been issued, subsequent bus read operations output the status register. see the status register section for details. during an erase all main blocks operation, only the read status register command is accepted by the memory; any other command are ignored. erase all main blocks, once started, cannot be suspended. the erase all main blocks command can be exe- cuted using v dd . if v pen is at v ih , the operation will be performed. if v pen is lower than v ih the op- eration aborts and the status register v pen bit (bit 3) is set to '1'. program command the program command is used to program the memory array. two bus write operations are re- quired to issue the command; the first write cycle sets up the program command, the second write cycle latches the address and data to be pro- grammed and starts the program/erase control- ler. a program operation can be aborted by writing ffffffffh to any address after the program set- up command has been given. the program command is also used to program the otp block. refer to table 8., commands , for details of the address. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the program operation the memory will only accept the read status register command and the pro- gram/erase suspend command. all other com- mands will be ignored. if reset/power-down, rp , falls to v il during pro- gramming the operation will be aborted. the command can be executed using v dd . if v pen is at v ih , the operation can be performed. if v pen goes below v ih, the operation aborts, the v pen status bit in the status register is set to ?1? and the command must be re-issued. see appendix a , figure 20., program flowchart and pseudo code , for a suggested flowchart on using the program command. write to buffer and program command the write to buffer and program command makes use of the device?s double word (32 bit) write buffer to speed up programming. up to eight double words can be loaded into the write buffer and programmed into the memory. four successive steps are required to issue the- command. 1. one bus write operation is required to set up the write to buffer and program command. any bus read operations will start to output the status register after the 1st cycle. 2. use one bus write operation to write the selected memory block address (any address in the block where the values will be programmed can be used) along with the value n on the data inputs/outputs, where n+1 is the number of words to be programmed. the maximum value of n+1 is 8 words. 3. use n+1 bus write operations to load the address and data for each word into the write buffer. the address must be between start address and start address plus n, where start address is the first word address. 4. finally, use one bus write operation to issue the final cycle to confirm the command and start the program operation. if any address is outside the block boundaries or if the correct sequence is not followed, status reg- ister bits 4 and 5 are set to ?1? and the operation will abort without affecting the data in the memory ar- ray. a protected block must be unprotected using the blocks unprotect command. during a write to buffer and program operation the memory will only accept the read status reg- ister and the program/erase suspend commands. all other commands are ignored. the write to buffer and program command can be executed using v dd . if v pen is at v ih , the operation will be performed. if v pen is lower than v ih the operation aborts and the status register v pen bit (bit 3) is set to '1'.
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 24/60 the status register should be cleared before re- issuing the command. program/erase suspend command the program/erase suspend command is used to pause a program or erase operation. the com- mand will only be accepted during a program or erase operation. it can be issued at any time dur- ing a program or erase operation. the command is ignored if the device is already in suspend mode. one bus write cycle is required to issue the pro- gram/erase suspend command and pause the program/erase controller. once the command is issued it is necessary to poll the program/erase controller status bit (bit 7) to find out when the program/erase controller has paused; no other commands will be accepted until the program/ erase controller has paused. after the program/ erase controller has paused, the memory will con- tinue to output the status register until another command is issued. during the polling period between issuing the pro- gram/erase suspend command and the program/ erase controller pausing it is possible for the op- eration to complete. once the program/erase controller status bit (bit 7) indicates that the pro- gram/erase controller is no longer active, the pro- gram suspend status bit (bit 2) or the erase suspend status bit (bit 6) can be used to deter- mine if the operation has completed or is suspend- ed. for timing on the delay between issuing the program/erase suspend command and the pro- gram/erase controller pausing see table 10 . during program/erase suspend the read memo- ry array, read status register, read electronic signature, read query and program/erase re- sume commands will be accepted by the com- mand interface. additionally, if the suspended operation was erase then the program, the write to buffer and program, the set/clear block protec- tion configuration register and the program sus- pend commands will also be accepted. when a program operation is completed inside a block erase suspend the read memory array command must be issued to reset the device in read mode, then the erase resume command can be issued to complete the whole sequence. only the blocks not being erased may be read or programmed cor- rectly. see appendix a , figure 21., program suspend & resume flowchart and pseudo code , and figure 23., erase suspend & resume flowchart and pseudo code , for suggested flowcharts on using the program/erase suspend command. program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the pro- gram/erase resume command. see appendix a , figure 21., program suspend & resume flowchart and pseudo code , and figure 23., erase suspend & resume flowchart and pseudo code , for suggested flowcharts on using the program/erase suspend command. set burst configuration register command. the set burst configuration register command is used to write a new value to the burst configura- tion register which defines the burst length, type, x and y latencies, synchronous/asynchronous read mode. two bus write cycles are required to issue the set burst configuration register command. the first cycle writes the setup command. the second cy- cle writes the address where the new burst con- figuration register content is to be written, and confirms the command. if the command is not con- firmed, the sequence is aborted and the device outputs the status register with bits 4 and 5 set to ?1?. once the command is issued the memory re- turns to read mode as if a read memory array command had been issued. the value for the burst configuration register is always presented on a0-a15. m0 is on a0, m1 on a1, etc.; the other address bits are ignored. tuning protection unlock command the tuning protection unlock command unlocks the tuning protected blocks by writing the 64bit tuning protection code (m58bw032b only). after a reset or power-up the blocks are locked and so a tuning protection unlock command must be is- sued to allow program or erase operations on tun- ing protected block or to program a new tuning protection code. read operations output the sta- tus register content after the unlock operation has started. the tuning protection code is composed of 64 bits, but the data bus is 32 bits wide so four (2 x 2) write cycles are required to unlock the device. the first write cycle issues the tuning protection unlock setup command (78h). the second write cycle inputs the first 32 bits of the tuning protection code on the data bus, at address 00000h. bit 7 of the status register should now be checked to verify that the device has successfully stored the first part of the code in the internal reg- ister. if b7 = ?1?, the device is ready to accept the second part of the code. this does not mean that the first 32 bits match the tuning protection code, simply that it was correctly stored for the compar- ing. if b7 = ?0?, the user must wait for this bit setting (refer to write cycle ac timings).
25/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db the third write cycle re-issues the tuning protection unlock setup command (78h). the fourth write cycle inputs the second 32 bits of the code at address 00001h. bit 7 of the status register should again be checked to verify that the device has successfully stored the second part of the code. when the de- vice is ready (b7 = ?1?), the tuning protection status can be monitored on status register bit0. if b0 = ?0? the device is locked; b0 = ?1? the device is un- locked. if the device is still locked a read memory array command must be issued before re-issuing the tuning protection unlock command. device locked means that the 64 bit password is wrong. if the unlock operation is attempted using a wrong code on an already unlocked device, the device becomes locked. status register bit 4 is set to '1' if there has been a verify failure. tuning protection unlock command aborts if v pen drops below v ih or rp goes to v il . once the device is successfully unlocked, a read memory array command must be issued to return the memory to read mode before issuing any other commands. the user can then program or erase all blocks, depending on wp and v pen status and on the protection status of each block. at this point, it is also possible to configure a new protec- tion code. to write a new protection code into the device tuning register, the user must perform the tuning protection program sequence. the device can be re-locked with a reset or power-down. see appendix a , figure 24 , 25 and 26 for suggest- ed flowcharts for using the tuning protection un- lock command. tuning protection program command. the tuning protection program command is used to program a new tuning protection code which can be configured by the designer of the applica- tion (m58bw032b only). the device should be un- locked by the tuning protection unlock command before issuing the tuning protection program command. read operations output the status register con- tent after the program operation has started. the tuning protection code is composed of 64 bits, but the data bus is 32 bits wide so four (2 x 2) write cycles are required to program the code. the first write cycle issues the tuning protection program setup command (48h). the second write cycle inputs the first 32 bits of the new tuning protection code on the data bus, at address 00000h. bit 7 of the status register should now be checked to verify that the device has successfully stored the first part of the code in the internal reg- ister. if b7 = ?1?, the device is ready to accept the second part of the code. if b7 = ?0?, the user must wait for this bit setting (refer to write cycle ac tim- ings). the third write cycle re-issues the tuning protection program setup command (48h). the fourth write cycle inputs the second 32 bits of the new code at address 00001h. bit 7 of the status register should again be checked to verify that the device has successfully stored the second part of the code. when the de- vice is ready (b7 = ?1?). after completion status register bit 4 is set to '1' if there has been a pro- gram failure. programming aborts if v pen drops below v ih or rp goes to v il . a read memory array command must be issued to return the memory to read mode before issuing any other commands. once the code has been changed a device reset or power-down will make the protection active with the new code. see appendix a , figure 24 , 25 and 26 for suggest- ed flowcharts for using the tuning protection pro- gram command. set block protection configuration register command the set block protection configuration register command is used to configure the block protec- tion configuration register to ?protected?, for a specific block. protected blocks are fully protected from program or erase when wp pin is low, v il . the status of a protected block can be changed to ?unprotected? by using the clear block protection configuration register command. at power-up, all block are configured as ?protected?. two bus operations are required to issue a set block protection configuration register com- mand: the first cycle writes the setup command the second write cycle specifies the address of the block to protect and confirms the command. if the command is not confirmed, the sequence is aborted and the device outputs the status register with bits 4 and 5 set to ?1?. to protect multiple blocks, the set block protec- tion configuration register command must be re- peated for each block. any attempt to re-protect a block already protected does not change its status. clear block protection configuration register command. the clear block protection configuration register command is used to configure the block protec- tion configuration register to ?unprotected?, for a
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 26/60 specific block thus allowing program/erase opera- tions to this block, regardless of the wp pin status. two bus operations are required to issue a clear block protection configuration register com- mand: the first cycle writes the setup command the second write cycle specifies the address of the block to unprotect and confirms the command. if the command is not confirmed, the sequence is aborted and the device outputs the status register with bits 4 and 5 set to ?1?. to unprotect multiple blocks, the clear block pro- tection configuration register command must be repeated for each block. any attempt to unprotect a block already unpro- tected does not affect its status. table 8. commands note: 1. x don?t care; ra read address, rd read data, id device code, ida identifier address, idd identifier data, srd status reg ister data, pa program address; pd program data, qa query address, qd query data, ba any address in the block, bcr burst con- figuration register value, tpa = tuning protection address, tpc = tuning protection code, n+1 number of words to program, ba block address. 2. the manufacturer code, the device code, the burst configurati on register, and the block protec tion configuration register of each block are read using the read electronic signature command. 3. cycles 1 and 2 input the first 32 bits of the code, cycles 3 and 4 the second 32 bits of the code. command cycles bus operations 1st cycle 2nd cycle 3rd cycle 4th cycle op. addr. data op. addr. data op. addr. data op. addr. data read memory array 2 write x ffh read ra rd read electronic signature (2) 2write x 90hread ida (1) idd (1) read status register 1 write x 70h read query 2 write x 98h read ra rd clear status register 1 write x 50h block erase 2 write 55h 20h write ba d0h erase all main blocks 2 write 55h 80h write aah d0h program any block 2 write aah 40h 10h write pa pd otp block 2 write aah 40h write pa pd write to buffer and program n+4 write aah e8h write ba n write pa pd write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h set burst configuration register 3 write x 60h write bcrh 03h read ra rd tuning protection program (3) 4 write aah 48h write tpah tpch write aah 48h write tpah tpch tuning protection unlock (3) 4 write x 78h write tpah tpch write x 78h write tpah tpch set block protection configuration register 2 write x 60h write ba 01h clear block protection configuration register 2 write x 60h write ba d0h
27/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db table 9. read electronic signature note: 1. x= b or d version of the device. 2. bcr= burst configuration register. 3. sba is the start address of each block. table 10. program, erase times and program erase endurance cycles note: t a = ?40 to 125c, v dd = 3.0v to 3.6v, v ddq = 1.6v to v dd code device a19-a0 dq31-dq0 manufacturer all 00000h 00000020h device m58bw032xt (1) 00001h 00008838h m58bw032xb (1) 00001h 00008837h burst configuration register 00005h bcr (2) block protection configuration register all sba+02h (3) 00000000h (unprotected) 00000001h (protected) parameters m58bw032b/d unit min typ max full chip program 15 20 s double word program tbd tbd s 512 kbit block erase 1 2 s 256 kbit block erase 0.8 1.6 s 64 kbit block erase 0.6 1.2 s program suspend latency time 3 10 s erase suspend latency time 10 30 s program/erase cycles (per block) 100,000 cycles
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 28/60 status register the status register provides information on the current or previous program, erase, block protect or tuning protection operation. the various bits in the status register convey information and errors on the operation. they are output on dq7-dq0. to read the status register the read status reg- ister command can be issued. the status register is automatically read after program, erase, block protect, program/erase resume commands. the status register can be read from any address. the contents of the status register can be updat- ed during an erase or program operation by tog- gling the output enable or output disable pins or by dis-activating (chip enable, v ih ) and then reac- tivating (chip enable and output enable, v il , and output disable, v ih .) the device. the status register bits are summarized in table 11., status register bits . refer to table 11 in con- junction with the following text descriptions. program/erase controller status (bit 7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller sta- tus bit is set to ?0?, the program/erase controller is active; when bit7 is set to ?1?, the program/erase controller is inactive. the program/erase controller status is set to ?0? immediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is set to ?1?. during program and erase operations the pro- gram/erase controller status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the pro- gram/erase controller completes the operation and the bit is set to ?1?. after the program/erase controller completes its operation the erase status (bit5), program/tuning protection unlock status (bit4) bits should be test- ed for errors. erase suspend status (bit 6) the erase suspend status bit indicates that an erase operation has been suspended and is wait- ing to be resumed. the erase suspend status should only be considered valid when the pro- gram/erase controller status bit is set to ?1? (pro- gram/erase controller inactive); after a program/ erase suspend command is issued the memory may still complete the operation rather than enter- ing the suspend mode. when the erase suspend status bit is set to ?0?, the program/erase controller is active or has com- pleted its operation; when the bit is set to ?1?, a pro- gram/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is is- sued the erase suspend status bit returns to ?0?. erase status (bit 5) the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. the erase status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). when the erase status bit is set to ?0?, the memory has successfully verified that the block has erased correctly. when the erase status bit is set to ?1?, the program/erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. once set to ?1?, the erase status bit can only be re- set to ?0? by a clear status register command or a hardware reset. if set to ?1? it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program/ write to buffer and program/tuning protection unlock status (bit 4) the program/write to buffer and program/tuning protection unlock status bit is used to identify a program failure, a write to buffer and program failure or a tuning protection code verify failure. bit4 should be read once the program/erase con- troller status bit is high (program/erase controller inactive). when bit4 is set to ?0? the memory has successful- ly verified that the device has programmed cor- rectly or that the correct tuning protection code has been written. when bit4 is set to ?1? the device has failed to verify that the data has been pro- grammed correctly or that the correct tuning pro- tection code has been written. once set to 1?, the program status bit can only be reset to ?0? by a clear status register command or a hardware reset. if set to ?1? it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. v pen status (bit 3). the v pen status bit can be used to identify if a program or erase operation has been attempted when v pen is low, v il . when bit 3 is set to ?0? no program or erase oper- ations have been attempted with v pen low, v il , since the last clear status register command, or hardware reset. when bit 3 is set to ?1? a program or erase opera- tion has been attempted with v pen low, v il . once set to ?1?, bit 3 can only be reset by an clear status register command or a hardware reset. if set to ?1? it should be reset before a new program
29/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db or erase command is issued, otherwise the new command will appear to fail. program suspend status (bit 2) the program suspend status bit indicates that a program operation has been suspended and is waiting to be resumed. the program suspend status should only be considered valid when the program/erase controller status bit is set to ?1? (program/erase controller inactive); after a pro- gram/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is set to ?0?, the program/erase controller is active or has com- pleted its operation; when the bit is set to ?1?, a pro- gram/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is is- sued the program suspend status bit returns to ?0?. block protection status (bit 1) the block protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a protected block. when the block protection status bit is set to ?0?, no program or erase operations have been at- tempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is set to ?1?, a program or erase operation has been attempted on a protected block. once set to ?1?, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set to ?1? it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail. tuning protection status (bit 0) the tuning protection status bit indicates if the device is locked (tuning protection is enabled) or unlocked (tuning protection is disabled). when the tuning protection status bit is set to ?0? the device is locked, when it is set to ?1? the device is unlocked. after a reset or power-up the device is locked and so bit0 is set to ?0?. the tuning protection status bit is set to ?1? for the m58bw032d version. table 11. status register bits note: 1. for the m58bw032d version the tuning protection status bit is always set to ?1?. bit name logic level definition 7 program/erase controller status ?1? ready ?0? busy 6 erase suspend status ?1? suspended ?0? in progress or completed 5 erase status ?1? erase error ?0? erase success 4 program status, tuning protection unlock status ?1? program error ?0? program success 3 v pen status bit ?0? no program or erase attempted ?1? program or erase attempted 2 program suspend status ?1? suspended ?0? in progress or completed 1 erase/program in a protected block ?1? program/erase on protected block, abort ?0? no operations to protected blocks 0 tuning protection status ?1? tuning protection disabled (1) ?0? tuning protection enabled
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 30/60 maximum rating stressing the device above the ratings listed in ta- ble 12., absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 12. absolute maximum ratings note: 1. compliant with the ecopack? 7191395 specification for lead-free soldering processes. symbol parameter value unit min max t bias temperature under bias ?40 125 c t stg storage temperature ?55 155 c t lead lead temperature during soldering (1) tbd c v io input or output voltage ?0.6 v ddq +0.6 v ddqin +0.6 v v dd , v ddq, v ddqin supply voltage ?0.6 4.2 v
31/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 13., operating and ac measurement conditions . designers should check that the operating condi- tions in their circuit match the measurement condi- tions when relying on the quoted parameters. table 13. operating and ac measurement conditions figure 6. ac measurement input output waveform note: v dd = v ddq . figure 7. ac measurement load circuit table 14. device capacitance note: 1. t a = 25c, f = 1 mhz 2. sampled only, not 100% tested. parameter value units min max supply voltage (v dd ) 3.0 3.6 v input/output supply voltage (v ddq ) 2.4 3.6 v ambient temperature (t a ) grade 6 ?40 90 c grade 3 ?40 125 c load capacitance (c l ) 30 pf clock rise and fall times 3 ns input rise and fall times 3 ns input pulses voltages 0 to v ddq v input and output timing ref. voltages v ddq /2 v ai04153 v ddq v ddqin 0v v ddq /2 v ddqin /2 ai04154b out c l c l includes jig capacitance device under test symbol parameter test condition typ max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 32/60 table 15. dc characteristics note: 1. the standby mode can be disabled by setting the standby dis able bit (m14) of the burst configuration register to ?1?. symbol parameter test condition min max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i dd (1) supply current (random read) e = v il , g = v ih , f add = 6mhz 50 ma i ddb (1) supply current (burst read) e = v il , g = v ih , f clock = 75mhz 50 ma i dd1 (1) supply current (standby) e = rp = v dd 0.2v 100 a i dd2 (1) supply current (program or erase) program, erase in progress 30 ma i dd3 (1) supply current (erase/program suspend) e = v ih 40 a v il input low voltage ?0.5 0.2v ddqin v v ih input high voltage (for dq lines) 0.8v ddqin v ddq +0.3 v v ih input high voltage (for input only lines) 0.8v ddqin 3.6 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage cmos i oh = ?100a v ddq ?0.1 v v lko v dd supply voltage (erase and program lockout) 2.2 v
33/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 8. asynchronous bus read ac waveforms table 16. asynchronous bus read ac characteristics. note: 1. output enable g may be delayed up to t elqv - t glqv after the falling edge of chip enable e without increasing t elqv . symbol parameter test condition m58bw032 unit 45 55 60 t avav address valid to address valid e = v il , g = v il min455560ns t avqv address valid to output valid e = v il , g = v il max455560ns t axqx address transition to output transition e = v il , g = v il min 0 ns t ehlx chip enable high to latch enable transition min 0 ns t ehqx chip enable high to output transition g = v il min 0 ns t ehqz chip enable high to output hi-z g = v il max 20 ns t elqv (1) chip enable low to output valid g = v il max455560ns t elqx chip enable low to output transition g = v il min 0 ns t ghqx output enable high to output transition e = v il min 0 ns t ghqz output enable high to output hi-z e = v il max 15 ns t glqv output enable low to output valid e = v il max 15 ns t glqx output enable to output transition e = v il min 0 ns t llel latch enable low to chip enable low min 0 ns ai08921 e g l a0-a19 dq0-dq31 valid tllel taxqx telqx telqv tavqv tglqx tglqv tehqx tehqz tghqx tghqz see also page read output tehlx tavav gd
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 34/60 figure 9. asynchronous latch controlled bus read ac waveforms table 17. asynchronous latch controlled bus read ac characteristics symbol parameter test condition m58bw032 unit 45 55 60 t avll address valid to latch enable low e = v il min000ns t ehlx chip enable high to latch enable transition min 0 0 0 ns t ehqx chip enable high to output transition g = v il min000ns t ehqz chip enable high to output hi-z g = v il max202020 ns t elll chip enable low to latch enable low min 0 0 0 ns t ghqx output enable high to output transition e = v il min000ns t ghqz output enable high to output hi-z e = v il max151515 ns t glqv output enable low to output valid e = v il max152525 ns t glqx output enable low to output transition e = v il min000ns t lhax latch enable high to address transition e = v il min555ns t lhll latch enable high to latch enable low min 10 10 10 ns t lllh latch enable low to latch enable high e = v il min101010 ns t llqv latch enable low to output valid e = v il , g = v il max455560 ns t llqx latch enable low to output transition e = v il , g = v il min000ns ai08922 l e g a0-a19 dq0-dq31 valid tehlx tlhll tlhax tavll telll tlllh tehqx tehqz tghqx ghqz tllqx tllqv tglqx tglqv see also page read output
35/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 10. asynchronous page read ac waveforms table 18. asynchronous page read ac characteristics note: for other timings see table 16., asynchronous bus read ac characteristics. . symbol parameter test condition m58bw032 unit 45 55 60 t avqv1 address valid to output valid e = v il , g = v il max252525 ns t axqx address transition to output transition e = v il , g = v il min 6 6 6 ns ai03646 a0-a1 dq0-dq31 a0 and/or a1 tavqv1 output taxqx output + 1
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 36/60 figure 11. asynchronous write ac waveform ai08923b dq0-dq31 w rp a0-a19 e = l g input valid valid twheh valid tavwh twlwh telwl input valid sr v pen twhax twhwl twhdx tdvwh twhgl twhqv tvphwh tqvvpl tqvpl tphwh rp = v dd rp = v hh read status register write cycle write cycle tavll
37/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 12. asynchronous latch controlled write ac waveform ai08924b dq0-dq31 w rp a0-a19 l g input valid valid valid tavlh input valid sr v pen tlhax read status register write cycle write cycle e tlllh tllwh twhax telwl twlwh twheh twhwl twhgl twhqv tdvwh twhdx tvphwh tqvvpl tqvpl rp = v hh rp = v dd tavwh telll tavll
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 38/60 table 19. asynchronous write and latch controlled write ac characteristics symbol parameter test condition m58bw032 unit 45 55 60 t avll address valid to latch enable low min 0 0 0 ns t avwh address valid to write enable high e = v il min252525ns t dvwh data input valid to write enable high e = v il min252525ns t elll chip enable low to latch enable low min 0 0 0 ns t elwl chip enable low to write enable low min 0 0 0 ns t lhax latch enable high to address transition min 5 5 5 ns t lllh latch enable low to latch enable high min 10 10 10 ns t llwh latch enable low to write enable high e = v il min252525ns t qvvpl output valid to v pen low min000ns t vphwh v pen high to write enable high min000ns t whax write enable high to address transition e = v il min000ns t whdx write enable high to input transition e = v il min000ns t wheh write enable high to chip enable high min 0 0 0 ns t whgl write enable high to output enable low min 150 150 150 ns t whqv write enable high to output valid min 175 175 175 ns t whwl write enable high to write enable low min 20 20 20 ns t wlwh write enable low to write enable high e = v il min252525ns t qvpl output valid to reset/power-down low min 0 0 0 ns
39/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 13. synchronous burst read (data valid from ?n? clock rising edge) ai08925b dq0-dq31 a0-a19 l e g k valid tkhax n+2 n+1 n 1 0 tkhll tllkh telll tavll tkhlx tehqx tehqz tghqx tghqz tglqv setup output tkhqv tavqv note : n depends on burst x-latency.
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 40/60 table 20. synchronous burst read ac characteristics note: 1. data output should be read on the valid clock edge. 2. for other timings see table 16., asynchronous bus read ac characteristics. . figure 14. synchronous burst read (data valid from ?n? clock rising edge) note: for set up signals and timings see synchronous burst read. symbol parameter test condition m58bw032 unit 45 55 60 t avll address valid to latch enable low e = v il min 0 0 0 ns t bhkh burst address advance high to valid clock edge e = v il , g = v il , l = v ih min 8 8 8 ns t blkh burst address advance low to valid clock edge e = v il , g = v il , l = v ih min 8 8 8 ns t elll chip enable low to latch enable low min 0 0 0 ns t glqv output enable low to output valid e = v il , l = v ih min101010ns t khax valid clock edge to address transition e = v il min 5 5 5 ns t khll valid clock edge to latch enable low e = v il min 0 0 0 ns t khlx valid clock edge to latch enable transition e = v il min 0 0 0 ns t khqx valid clock edge to output transition e = v il , g = v il , l = v ih min 0 0 0 ns t llkh latch enable low to valid clock edge e = v il min 6 6 6 ns t rlkh valid data ready low to valid clock edge e = v il , g = v il , l = v ih min 6 6 6 ns t khqv valid clock edge to output valid e = v il , g = v il , l = v ih max 8 8 8 ns ai04408c k n+5 n+4 n+3 n+2 n+1 n dq0-dq31 tkhqx q0 q1 q2 q3 q4 q5 setup burst read q0 to q3 tkhqv note: n depends on burst x-latency
41/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 15. synchronous burst read - continuous - valid data ready output note: valid data ready = valid low during valid clock edge 1. v= valid output. 2. the internal timing of r follows dq. figure 16. synchronous burst read - burst address advance ai03649b k output (1) vvvv trlkh r v (2) ai03650 k q0 q1 l q2 valid g tglqv tblkh tbhkh b dq0-dq31 a0-a19
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 42/60 figure 17. reset, power-down and power-up ac waveform table 21. reset, power-down and power-up ac characteristics note: 1. this time is t phel + t avqv or t phel + t elqv . symbol parameter min max unit t phel reset/power-down high to chip enable low 50 ns t phqv (1) reset/power-down high to output valid 130 ns t phwl reset/power-down high to write enable low 50 ns t phgl reset/power-down high to output enable low 50 ns t plph reset/power-down low to reset/power-down high 100 ns t plrh reset/power-down low to valid data ready high 2 30 s t vdhph supply voltages high to reset/power-down high 10 s ai03849b w, rp tphwl tphel tphgl e, g vdd, vddq tvdhph tphwl tphel tphgl tplph tplrh power-up reset r
43/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db package mechanical figure 18. lbga80 10x12mm - 8x10 ball array, 1mm pitch, bottom view package outline note: drawing is not to scale. table 22. lbga80 10x12mm - 8x10 ball array, 1mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.700 0.0669 a1 0.400 0.350 0.450 0.0157 0.0138 0.0177 a2 1.100 0.0433 b 0.500 ? ? 0.0197 ? ? d10.000? ?0.3937? ? d1 7.000 ? ? 0.2756 ? ? ddd 0.150 0.0059 e12.000? ?0.4724? ? e1 9.000 ? ? 0.3543 ? ? e 1.000 ? ? 0.0394 ? ? fd 1.500 ? ? 0.0591 ? ? fe 1.500 ? ? 0.0591 ? ? sd 0.500 ? ? 0.0197 ? ? se 0.500 ? ? 0.0197 ? ? e1 e d1 d eb a2 a1 a bga-z05 ddd fd fe sd se e ball "a1"
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 44/60 figure 19. pqfp80 - 80 lead plastic quad flat pack, package outline note: drawing is not to scale. table 23. pqfp80 - 80 lead plastic quad flat pack, package mechanical data symbol millimeters inches typ min max typ min max a 3.400 0.1339 a1 0.250 0.0098 a2 2.800 2.550 3.050 0.1102 0.1004 0.1201 b 0.300 0.450 0.0118 0.0177 c 0.130 0.230 0.0051 0.0091 d 23.200 22.950 23.450 0.9134 0.9035 0.9232 d1 20.000 19.900 20.100 0.7874 0.7835 0.7913 d2 18.400 ? ? 0.7244 ? ? e 0.800 ? ? 0.0315 ? ? e 17.200 16.950 17.450 0.6772 0.6673 0.6870 e1 14.000 13.900 14.100 0.5512 0.5472 0.5551 e2 12.000 ? ? 0.4724 ? ? l 0.800 0.650 0.950 0.0315 0.0256 0.0374 l1 1.600 ? ? 0.0630 ? ? 0 7 0 7 n80 80 nd 24 24 ne 16 16 qfp-b d1 cp b e a2 a n l a1 e1 e2 1 d c e d2 l1 nd ne
45/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db part numbering table 24. ordering information scheme note: devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m58bw032b t 45 t 3 t device type m58 architecture b = burst mode operating voltage w = v dd = 3.0v to 3.6v; v ddq = v ddqin =1.6 to v dd device function 032b = 32 mbit (x32), boot block, burst tuning protection 032d = 32 mbit (x32), boot block, burst no tuning protection array matrix t = top boot b = bottom boot speed 45 = 45ns 55 = 55ns 60 = 60ns package t = pqfp80 za = lbga80: 1.0mm pitch temperature range 3 = ?40 to 125 c 6 = ?40 to 85 c option t = tape & reel packing
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 46/60 appendix a. flow charts figure 20. program flowchart and pseudo code note: 1. if an error is found, the status register must be cleared before further p/e operations. write 40h ai03850d start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pen invalid error (1) program error (1) program command: ? write 40h, address aah ? write address & data (memory enters read status state after the program command) do: ? read status register (e or g must be toggled) while b7 = 1 if b3 = 1, v pen invalid error: ? error handler if b4 = 1, program error: ? error handler yes end no b1 = 0 program to protect block error if b1 = 1, program to protected block error: ? error handler yes
47/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 21. program suspend & resume flowchart and pseudo code write 70h ai00612b read status register yes no b7 = 1 yes no b2 = 1 program continues write ffh program/erase suspend command: ? write b0h ? write 70h do: ? read status register while b7 = 1 if b2 = 0, program completed read memory array command: ? write ffh ? one or more data reads from other blocks write d0h program erase resume command: ? write d0h to resume programming ? if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend command was not issued). read data from another block start write b0h program complete write ffh read data
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 48/60 figure 22. block erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared before further p/e operations. write 20h ai08623c start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 yes b4 and b5 = 1 v pen invalid error (1) command sequence error erase command: ? write 20h, address 55h ? write block address (a11-a19) & d0h (memory enters read status state after the erase command) do: ? read status register (e or g must be toggled) if erase command given execute suspend erase loop while b7 = 1 if b3 = 1, v pen invalid error: ? error handler if b4, b5 = 1, command sequence error: ? error handler no no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: ? error handler yes end yes no b1 = 0 erase to protected block error if b1 = 1, erase to protected block error: ? error handler
49/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 23. erase suspend & resume flowchart and pseudo code write 70h ai00615b read status register yes no b7 = 1 yes no b6 = 1 erase continues write ffh program/erase suspend command: ? write b0h ? write 70h do: ? read status register while b7 = 1 if b6 = 0, erase completed read memory array command: ? write ffh ? one or more data reads from other blocks write d0h read data from another block or program start write b0h erase complete write ffh read data program/erase resume command: ? write d0h to resume the erase operation ? if the erase operation completed then this is not necessary. the device returns to read mode as normal (as if the program/erase suspend was not issued).
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 50/60 figure 24. unlock device and change tuning protection code flowchart ai04501b reset device locked by tuning code 1st: write cycle 2nd: write cycle (old code, factory setup = ffffh) yes 3rd: write cycle 4th: write cycle (old code, factory setup = ffffh) yes yes no device locked add: aah data: 48h 6th: write cycle add: 00000h data: first 32 bit 7th: write cycle (new code) yes b7 = 1 add: aah data: 48h 8th: write cycle add: 00001h data: second 32 bit 9th: write cycle (new code) yes b7 = 1 device unlocked reset device locked by new code tuning protection unlock sequence add: don't care data: ffh 5th: write cycle issue read command issue read command add: don't care data: 78h add: 00000h data: first 32 bit b7 = 1 add: don't care data: 78h add: 00001h data: second 32 bit b7 = 1 read status register b0 = 1 add: don't care data: ffh
51/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 25. unlock device and program a tuning protected block flowchart ai04502b reset device locked by tuning code add: don't care data: 78h 1st: write cycle add: 00000h data: first 32 bit 2nd: write cycle (first part of the tuning code) yes b7 = 1 add: don't care data: 78h 3rd: write cycle add: 00001h data: second 32 bit 4th: write cycle (second part of the tuning code) yes b7 = 1 yes no b0 = 1 device locked add: aah data: 40h 6th: write cycle add: location to prog. data: data to prog. 7th: write cycle yes b7 = 1 device unlocked status register check location programmed tuning protection unlock sequence add: don't care data: ffh issue read command 5th: write cycle add: don't care data: ffh issue read command read status register
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 52/60 figure 26. unlock device and erase a tuning protected block flowchart ai04503b reset device locked by tuning code add: don't care data: 78h 1st: write cycle add: 00000h data: first 32 bit 2nd: write cycle (first part of the tuning code) yes b7 = 1 add: don't care data: 78h 3rd: write cycle add: 00001h data: second 32 bit 4th: write cycle (second part of the tuning code) yes b7 = 1 yes no b0 = 1 device locked add: 55h data: 20h 6th: write cycle add: block to erase data: d0h 7th: write cycle yes b7 = 1 device unlocked status register check block erased tuning protection unlock sequence add: don't care data: ffh issue read command 5th: write cycle add: don't care data: ffh issue read command read status register
53/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 27. power-up sequence to burst the flash ai03834 power-up or reset asynchronous read write 60h command write 03h with a15-a0 bcr inputs synchronous read bcr bit 15 = '1' set burst configuration register command: ? write 60h ? write 03h and bcr on a15-a0 bcr bit 15 = '0' bcr bit 14-bit 0 = '1'
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 54/60 figure 28. command interface and program erase controller flowchart (a) ai03835 read elec. signature yes no 90h read status yes 70h no erase set-up yes 20h no program set-up yes 40h no clear status yes 50h no wait for command write read status read array yes d b c read cfi yes 98h no no d0h a erase command error e d
55/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 29. command interface and program erase controller flowchart (b) ai03836 tp program set_up yes no 48h set bcr set_up yes 60h no d tp unlock set_up yes 78h no ffh 03h no yes no e f g yes
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 56/60 figure 30. command interface and program erase controller flowchart (c) read status 70h b erase ready no a b0h no read status yes ready no erase suspend yes read array yes erase suspended read status yes no 40h no d0h no program set_up ai03837 yes yes no yes read status c
57/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 31. command interface and program erase controller flowchart (d) read status 70h b program ready no c b0h no read status yes ready no program suspend read array yes program suspended read status yes no no d0h ai03838 yes no yes read status yes
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 58/60 figure 32. command interface and program erase controller flowchart (e) b tp program ready f no read status ai03839 yes b tp unlock ready g no read status yes
59/60 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db revision history table 25. document revision history date version revision details 20-oct-2003 1.0 first issue. 21-oct-2003 1.1 figure 7, ac measurement load circuit modified. i ddb test condition updated in table 5, dc characteristics. 20-nov-2003 1.2 bit m3 no longer reserved, described in burst configuration register section. minor text changes. program and erase suspend latency times added to table table 10., program, erase times and program erase endurance cycles . 27-apr-2004 2.0 a19 added in figure 4.pqfp connections (top view through package) . table 6.burst configuration register , note 1 updated. 30-july-2004 3.0 dq8-dq15 and r signal names updated in table 1., signal names. description of valid data ready (r). signal updated. burst length bit (m2-m0). paragraph updated in burst configuration register section. x-latency of 8 clock cycles added in table 6., burst configuration register command interface section: erase all main blocks command added, read electronic signature command , read status register command , write to buffer and program command , set block protection configuration register command and clear block protection configuration register command. updated. erase all main blocks command added, write to buffer and program, set burst configuration register, set and clear block protection commands updated in table 8., commands . standby status removed from table 9., read electronic signature . definition of bit 4 updated in status register section. t qvkh removed from figure 13., synchronous burst read (data valid from ?n? clock rising edge) . 05-nov-2004 4.0 datasheet status changed to preliminary data.
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 60/60 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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